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BIOS Intel® Server Board SE7501WV2 TPS
Revision 1.0
Intel reference number C25653-001
74
6.3.3 ECC Initialization
Because only ECC memory is supported, the BIOS must initialize all memory locations before
using them. The BIOS uses the auto-initialize feature of the MCH to initialize ECC.
6.3.4 Memory Remapping
During POST memory testing, the detection of single-bit and multi-bit errors in DIMM banks is
enabled. If a single-bit error is detected, a single DIMM number will be identified. If a multiple-bit
error is detected, a bank of DIMMs will be identified. The BIOS logs all memory errors into the
System Event Log (SEL).
If an error is detected, the BIOS will reduce the usable memory so that the byte containing the
error is no longer accessible. This prevents a single-bit error (SBE) from becoming a multi-bit
error (MBE) after the system has booted, and it prevents SBEs from being detected and logged
each time the failed location(s) are accessed. This is done automatically by the BIOS during
POST. User intervention is not required.
Memory remapping can occur during base memory testing or during extended memory testing.
If remapping occurs during the base memory testing, the SEL event is not logged until after the
BIOS remaps the memory and successfully configures and tests 8 MB of memory. In systems
where all memory is found to be unusable, only the BIOS beep codes indicate the memory
failure. Once the BIOS locates a functioning bank of memory, remapping operations and other
memory errors are logged into the SEL and reported to the user at the completion of POST.
6.3.5 DIMM Failure LED
The SE7501WV2 server board provides DIMM failure LEDs located next to each DIMM slot on
the baseboard. The DIMM failure LEDs are used to indicate double-bit DIMM errors. If a double-
bit error is detected during POST, the BIOS sends a Set DIMM State command to the BMC
indicating that the DIMM LED is lit. These LED’s will only be reset when a Front Panel Reset is
performed with main power available to the system.
6.4 Processors
The BIOS determines the processor stepping, cache size, etc., through the CPUID instruction.
The requirements are that all processors in the system must operate at the same frequency and
have the same cache sizes. No mixing of product families is supported:
• If two 400MHz processors are installed, the system will run with a Front Side Bus Speed
(FSB) of 400MHz
• If two 533MHz processors are installed, the system will run with a FSB of 533MHz.
Processors run at a fixed speed and cannot be programmed to operate at a lower or higher
speed.
6.5 Extended System Configuration Data (ESCD), Plug and Play
(PnP)
The system BIOS supports industry standards for making the system Plug-and-Play ready.
Refer to the following reference documents: