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Block Diagram Descriptions
CSA 803C Service Manual
3Ć19
I/O Delayed Data Buffer
This circuit is the interface between the I/O data bus and the Write Delayed
data bus.
Timer Configuration
This circuitry is composed of a latch and three twoĆinput data multiplexers
built with discrete gates. When a byte of data on the I/O data bus is latched,
some of the data bits individually configure counters 1 and 2, allowing the
timer to accept different inputs for different system tasks. The operating
system uses counter 0 as a realĆtime clock based on the 2 MHz CLK input
from the clock generator that is always operating at 8 MHz.
Real Time Clock
This clock and its oscillator circuit maintain the current time of day. The EXP
sets the real time clock and also interrupts the Executive processor (EXP)
every one second to request the EXP to read the time.
Serial Data Interface (SDI)
This is a custom IC that interfaces the EXP to both front panel knobs. The
EXP controls this IC, and this IC interrupts the EXP when a device requires
service.
Tone Generator
This circuitry utilizes a DAC and a timer. The timer is equipped with a special
current switch and capacitor to set the timer's frequency. The timer outputs
a square wave whose frequency is inversely proportional to the digital value
written to the temp/tone DAC. Thus, if a zero value is input to the DAC, the
tone generator produces the highest tone.
Temp/Tone Readback Buffer
This circuit is an eightĆline buffer connected to the I/O data bus. The EXP
uses this buffer to monitor the tone generator.