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Block Diagram Descriptions
Theory of Operation
3Ć20
The A15 MMU board consists of the following circuits:
H MMU IC
H Waveform RAM
H Display interface
H Time Base/Controller interface
H Executive processor (EXP) interface
H Display IC
H Microprocessor
H Bit map RAM
H Waveform display RAM circuitry
H Video DAC
The A15 MMU board coordinates communications among the following
three CSA 803C subsystems:
H Display
H Time Base/Controller
H Executive
See Figure 9Ć9 for a block diagram of this board.
MMU IC
This circuit controls all data transfers to and from waveform RAM. The MMU
gate array controls highĆspeed transfers of waveform data and communicaĆ
tion messages between waveform RAM and the three subsystem interfaces:
the Display, Time Base/Controller and Executive processors. A set of handĆ
shaking lines designed to the DMA facilities of each particular subsystem
coordinates each subsystem interface.
Waveform RAM
This circuit consists of 512 Kbytes of RAM. The RAM holds waveform data
and messages that are read and written by the Time Base/Controller, DisĆ
play, and Executive subsystems.
Display Interface
Data is transferred to and from the Display subsystem and to and from the
MMU IC through this interface. The data is buffered with the bidirectional
display data buffers.
A15 Memory
Management Unit
(MMU) Board