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Block Diagram Descriptions
CSA 803C Service Manual
3Ć25
EPROMs, SRAM, and NVRAM
The memory includes EPROMs, System RAM (SRAM), and NonĆvolatile RAM
(NVRAM). The EPROMs contain all of the operating system code and diagĆ
nostics code for the EXP. All the memories share the latched address bus.
The SRAM (System RAM) stores miscellaneous constants that the operating
system code uses and produces. The NVRAM (nonĆvolatile RAM) contains
stored settings, stored traces, and other nonĆvolatile parameters. The meĆ
mories are organized into high and lowĆbyte pairs. The address decode PAL
generates latched chipĆselect signals. A separate latched chipĆselect signal
selects each of these pair. The memory data buffers buffer the data lines to
the Executive data bus.
Memory Data Buffers
This circuitry drives data between the memories and Executive data bus.
Both 8Ćbit buffers are enabled when all of their inputs are high.
Wait State Generator
This circuit allows the EXP to access memory devices when the EXP is
operating at faster clock frequencies. When the EXP is operating at frequenĆ
cies greater than 8 MHz, the bus cycle time is too short to allow reads or
writes to the present memory devices. The wait state generator sets the
SRDY line (see Figure 9Ć10) on the Executive bus low to signal the EXP to
lengthen the bus cycles.
The wait state generator also contains a circuit to generate control signals
(similar to those on the Executive bus). These control signals are early
address latch (ELATCH), early memory write control (EMWTC), and early
memory read control (EMRDC).
Wait State Diagnostics
These diagnostics measure the time interval that the wait state generator
generates when a one (1) is written to I/O address 8020
hex
. This causes the
wait state diagnostics to connect the SRDY signal to the DIAGNSIG line on
the Executive bus. A timer on the A14 I/O board can then measure the
length of the wait.
Memory Configuration Readback
This circuitry allows the diagnostics to read the position of the memory
configuration straps and the bank address lines. One bit of the readback
data byte also indicates if the battery is at 2.5 V (an early warning of a low
battery). The EXP performs an I/O read at address 8040
hex
to read this
information.