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22.3.4 Receive Packet Bytes Available ...............................................................................................144
22.3.5 HDLC FIFOS....................................................................................................................................145
22.4 RECEIVE HDLC CODE EXAMPLE............................................................................................................. 146
22.5 LEGACY FDL SUPPORT (T1 MODE)......................................................................................................... 146
22.5.1 Receive Section..............................................................................................................................146
22.5.2 Transmit Section.............................................................................................................................148
22.6 D4/SLC–96 OPERATION............................................................................................................................ 148
23. LINE INTERFACE UNIT (LIU)................................................................................................................149
23.1 LIU OPERATION.......................................................................................................................................... 150
23.2 LIU RECEIVER............................................................................................................................................. 150
23.2.1 Receive Level Indicator............................................................... Error! Bookmark not defined.
23.2.2 Receive G.703 Synchronization Signal (E1 Mode)............................................................151
23.2.3 Monitor Mode...................................................................................................................................151
23.3 LIU TRANSMITTER..................................................................................................................................... 152
23.3.1 Transmit Short-Circuit Detector/Limiter..................................................................................152
23.3.2 Transmit Open-Circuit Detector................................................................................................152
23.3.3 Transmit BPV Error Insertion .....................................................................................................152
23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)...........................................................152
23.4 MCLK PRESCALER..................................................................................................................................... 153
23.5 JITTER ATTENUATOR.................................................................................................................................. 153
23.6 CMI (CODE MARK INVERSION) OPTION ................................................................................................. 153
23.7 LIU CONTROL REGISTERS......................................................................................................................... 154
23.8 RECOMMENDED CIRCUITS......................................................................................................................... 164
23.9 COMPONENT SPECIFICATIONS................................................................................................................... 166
24. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION................170
25. BERT FUNCTION.......................................................................................................................................177
25.1 BERT REGISTER DESCRIPTION................................................................................................................. 178
25.2 BERT REPETITIVE PATTERN SET............................................................................................................. 183
25.3 BERT BIT COUNTER.................................................................................................................................. 184
25.4 BERT ERROR COUNTER............................................................................................................................ 185
26. PAYLOAD ERROR INSERTION FUNCTION...................................................................................186
26.1 NUMBER OF ERROR REGISTERS............................................................................................................... 188
26.1.1 Number Of Errors Left Register................................................................................................189
27. INTERLEAVED PCM BUS OPERATION...........................................................................................190
27.1 CHANNEL INTERLEAVE MODE.................................................................................................................. 190
27.2 FRAME INTERLEAVE MODE....................................................................................................................... 190
28. EXTENDED SYSTEM INFORMATION BUS (ESIB)......................................................................193
29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER......................................................197
30. FRACTIONAL T1/E1 SUPPORT...........................................................................................................198
31. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT.........................199
31.1 INSTRUCTION REGISTER............................................................................................................................. 203
31.2 TEST REGISTERS.......................................................................................................................................... 205
31.3 BOUNDARY SCAN REGISTER..................................................................................................................... 205
31.4 BYPASS REGISTER...................................................................................................................................... 205
31.5 IDENTIFICATION REGISTER........................................................................................................................ 205
32. FUNCTIONAL TIMING DIAGRAMS....................................................................................................208
32.1 T1 MODE...................................................................................................................................................... 208