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22. HDLC CONTROLLERS
This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is
configurable for use with time slots, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). Each HDLC
controller has 128 byte buffers in both the transmit and receive paths. When used with time slots, the user
can select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits
within the time slot(s) to assign to the HDLC controllers.
The user must take care to not map both transmit HDLC controllers to the same Sa bits, time slots or, in
T1 mode, map both controllers to the FDL. HDLC #1 and HDLC #2 are identical in operation and
therefore the following operational description refers only to a singular controller.
The HDLC controller performs all the necessary overhead for generating and receiving Performance
Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream.
The 128-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or
transmitted without host intervention.
22.1 Basic Operation Details
To allow the framer to properly source/receive data from/to the HDLC controllers, the legacy FDL
circuitry (See the Legacy FDL Support (T1 Mode) section.) should be disabled.
The HDLC registers are divided into four groups: control/configuration, status/information, mapping, and
FIFOs. Table 24-1 lists these registers by group.