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27. INTERLEAVED PCM BUS OPERATION
In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses
to simplify transport across the system backplane. The DS21Q55 can be configured to allow PCM data to
be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The
DS21Q55 can be configured for channel or frame interleave.
The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096MHz bus speed allows two
PCM data streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to
share a common bus. The 16.384MHz bus speed allows eight PCM data streams to share a common bus.
See Figure 30-1 for an example of four transceivers sharing a common 8.192MHz PCM bus. The receive
elastic stores of each transceiver must be enabled. Via the IBO register the user can configure each
transceiver for a specific bus position. For all IBO bus configurations each transceiver is assigned an
exclusive position in the high-speed PCM bus. The 8kHz frame sync can be generated from the system
backplane or from the first device on the bus. All other devices on the bus must have their frame syncs
configured as inputs. Relative to this common frame sync, the devices will await their turn to drive or
sample the bus according to the settings of the DA0, DA1, and DA2 bits of the IBOC register.
27.1 Channel Interleave Mode
In channel interleave mode, data is output to the PCM data-out bus one channel at a time from each of the
connected devices until all channels of frame n from each device has been placed on the bus. This mode
can be used even when the DS21Q55s are operating asynchronous to each other. The elastic stores will
manage slip conditions.
27.2 Frame Interleave Mode
In frame interleave mode, data is output to the PCM data-out bus one frame at a time from each of the
devices. This mode is used only when all connected devices are operating in a synchronous fashion (all
inbound T1 or E1 lines are synchronous) and are synchronous with the system clock (system clock
derived from T1 or E1 line). In this mode, slip conditions are not allowed.