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INTEL BUS READ TIMING (BTS = 0 / MUX = 1) Figure 37-1
INTEL BUS WRITE TIMING (BTS = 0 / MUX = 1) Figure 37-2
ASH
PW
t
CYC
t
ASD
t
ASD
PW
PW
EH
EL
t
t
t
t
t
t
AHL
CH
CS
ASL
ASED
CS*
AD0-AD7
DHR
t
DDR
ALE
RD*
WR*
ASH
PW
t
CYC
t
ASD
t
ASD
PW
PW
EH
EL
t
t
t
t
t
t
t
AHL
DSW
DHW
CH
CS
ASL
ASED
CS*
AD0-AD7
RD*
WR*
ALE