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12. LOOPBACK CONFIGURATION.............................................................................................................68
12.1 PER-CHANNEL LOOPBACK...........................................................................................................................70
13. ERROR COUNT REGISTERS .................................................................................................................72
13.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) ..............................................................................73
13.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) .............................................................................75
13.3 FRAMES OUT OF SYNC COUNT REGISTER (FOSCR) ...............................................................................76
13.4 E-BIT COUNTER REGISTER (EBCR) ...........................................................................................................78
14. DS0 MONITORING FUNCTION..............................................................................................................79
14.1 TRANSMIT DS0 MONITOR REGISTERS........................................................................................................79
14.2 RECEIVE DS0 MONITOR REGISTERS...........................................................................................................80
15. SIGNALING OPERATION.........................................................................................................................81
15.1 RECEIVE SIGNALING......................................................................................................................................81
15.1.1 Processor-Based Receive Signaling.........................................................................................82
15.1.2 Hardware-Based Receive Signaling..........................................................................................82
15.2 TRANSMIT SIGNALING...................................................................................................................................87
15.2.1 Processor-Based Transmit Signaling........................................................................................87
15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode.......................................93
15.2.3 Software Signaling Insertion Enable Registers, T1 Mode..................................................95
16. PER-CHANNEL IDLE CODE GENERATION.....................................................................................97
16.1 IDLE CODE PROGRAMMING EXAMPLES......................................................................................................98
17. CHANNEL BLOCKING REGISTERS..................................................................................................103
18. ELASTIC STORES OPERATION.........................................................................................................106
18.1 RECEIVE SIDE.............................................................................................................................................. 110
18.1.1 T1 Mode............................................................................................................................................110
18.1.2 E1 Mode ............................................................................................................................................110
18.2 TRANSMIT SIDE........................................................................................................................................... 111
18.2.1 T1 Mode............................................................................................................................................111
18.2.2 E1 Mode ............................................................................................................................................111
18.3 ELASTIC STORES INITIALIZATION............................................................................................................. 111
18.4 MINIMUM-DELAY MODE........................................................................................................................... 111
19. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................113
20. T1 BIT ORIENTED CODE (BOC) CONTROLLER .........................................................................114
20.1 TRANSMIT BOC .......................................................................................................................................... 114
20.2 RECEIVE BOC ............................................................................................................................................. 114
21. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY).................118
21.1 HARDWARE SCHEME (METHOD 1)........................................................................................................... 118
21.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (METHOD 2).......................................... 118
21.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME (METHOD 3)................................... 121
22. HDLC CONTROLLERS ............................................................................................................................132
22.1 BASIC OPERATION DETAILS...................................................................................................................... 132
22.2 HDLC CONFIGURATION............................................................................................................................ 134
22.2.1 FIFO Control ....................................................................................................................................136
22.3 HDLC MAPPING......................................................................................................................................... 137
22.3.1 Receive..............................................................................................................................................137
22.3.2 Transmit.............................................................................................................................................139
22.3.3 FIFO Information............................................................................................................................144