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RECEIVE SIDE ESF TIMING Figure 35-2
NOTES:
1) RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is not enabled (IOCR1.6 = 0).
2) RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is enabled (IOCR1.6 = 1).
3) RSYNC in multiframe mode (IOCR1.4 = 1).
4) ZBTSI mode disabled (T1RCR2.2 = 0).
5) RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames.
6) ZBTSI mode is enabled (T1RCR2.2 = 1).
7) RLINK data (Z bits) is updated one bit time before odd frames and held for four frames.
1 2 3 4 5 6 7 8 9 10 11 12
1
2
3
6
RFSYNC
FRAME#
TLCLK
RSYNC
RSYNC
RSYNC
TLINK
13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5
4
RLCLK
RLINK
5
7