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23.2.1 Receive Level Indicator and Threshold Interrupt
The DS21Q55 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0
located in Information Register 2 (INFO2). This feature is helpful when trouble-shooting line-
performance problems. The DS2155 can initiate an interrupt whenever the input falls below a certain
level through the input-level under-threshold indicator (SR1.7). Using the RLT0–RLT4 bits of the CCR4
register, the user can set a threshold in 2.5dB increments. The SR1.7 bit is set whenever the input level at
RTIP and RRING falls below the threshold set by the value in RLT0–RLT4. The level must remain
below the programmed threshold for approximately 50ms for this bit to be set.
23.2.2 Receive G.703 Synchronization Signal (E1 Mode)
The DS21Q55 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in
Section 13 of ITU G.703 10/98. In order to use this mode, set the receive synchronization clock Enable
(LIC3.2) = 1.
23.2.3 Monitor Mode
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS21Q55 can be programmed to support these applications via the monitor mode control bits MM1
and MM0 in the LIC3 register (Figure 25-2).
TYPICAL MONITOR APPLICATION Figure 25-2
PRIMARY
T1/E1 TERMINATING
DEVICE
MONITOR
PORT JACK
T1/E1 LINE
X
F
M
R
DS21Q55
Rt
Rm
Rm
SECONDARY T1/E1
TERMINATING
DEVICE