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TABLE OF CONTENTS
1.1 FEATURE HIGHLIGHTS ............................................................................................................................4
1.1.1 General .................................................................................................................................................. 4
1.1.2 Line Interface....................................................................................................................................... 4
1.1.3 Clock Synthesizer .............................................................................................................................. 4
1.1.4 Jitter Attenuator................................................................................................................................... 4
1.1.5 Framer/Formatter............................................................................................................................... 5
1.1.6 System Interface................................................................................................................................. 5
1.1.7 HDLC Controllers ............................................................................................................................... 6
1.1.8 Test and Diagnostics........................................................................................................................ 6
1.1.9 Extended System Information Bus............................................................................................... 6
1.1.10 Control Port .......................................................................................................................................... 6
1.2 DOCUMENT REVISION HISTORY.......................................................................................................12
2. BLOCK DIAGRAM ...........................................................................................................................................13
3. PIN FUNCTION DESCRIPTION..................................................................................................................14
3.1 TRANSMIT SIDE PINS.....................................................................................................................................14
3.2 RECEIVE SIDE PINS........................................................................................................................................16
3.3 PARALLEL CONTROL PORT PINS.................................................................................................................18
3.4 EXTENDED SYSTEM INFORMATION BUS.....................................................................................................20
3.5 JTAG TEST ACCESS PORT PINS...................................................................................................................20
3.6 LINE INTERFACE PINS....................................................................................................................................21
3.7 SUPPLY PINS...................................................................................................................................................22
3.8 PINOUT ............................................................................................................................................................23
3.9 PACKAGE.........................................................................................................................................................29
4. PARALLEL PORT ............................................................................................................................................30
4.1 REGISTER MAP ...............................................................................................................................................30
5. SPECIAL PER-CHANNEL REGISTER OPERATION.........................................................................36
6. PROGRAMMING MODEL..............................................................................................................................38
6.1 POWER-UP SEQUENCE ..................................................................................................................................39
6.1.1 Master Mode Register ....................................................................................................................39
6.2 INTERRUPT HANDLING..................................................................................................................................40
6.3 STATUS REGIST ERS........................................................................................................................................40
6.4 INFORMATION REGISTERS............................................................................................................................41
6.5 INTERRUPT INFORMATION REGISTERS........................................................................................................41
7. CLOCK MAP.......................................................................................................................................................42
8. T1 FRAMER/FORMATTER CONTROL REGISTERS .........................................................................43
8.1 T1 CONTROL REGISTERS..............................................................................................................................43
8.2 T1 TRANSMIT TRANSPARENCY....................................................................................................................48
8.3 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION.................................................................48
8.4 T1 INFORMATION REGISTER........................................................................................................................50
9. E1 FRAMER/FORMATTER CONTROL REGISTERS.........................................................................52
9.1 E1 CONTROL REGISTERS..............................................................................................................................52
9.2 AUTOMATIC ALARM GENERATION .............................................................................................................56
9.3 E1 INFORMATION REGISTERS.......................................................................................................................57
10. COMMON CONTROL AND STATUS REGISTERS.........................................................................59
11. I/O PIN CONFIGURATION OPTIONS...................................................................................................66