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information.
Register Name: SR1
Register Description: Status Register 1
Register Address: 16h
Bit # 7 6 5 4 3 2 1 0
Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC
Default 0 0 0 0 0 0 0 0
Bit 0/Loss of Line Interface Transmit Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel
time.
Bit 1/Transmit Open Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are
open-circuited.
Bit 2/Transmit Current Limit Exceeded Condition (TCLE). Set when the 50mA (rms) current limiter is activated whether
the current limiter is enabled or not.
Bit 3/Line Interface Receive Carrier Loss Condition (LRCL). Set when the carrier signal is lost.
Bit 4/Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its useful
limit. Will be cleared when read. Useful for debugging jitter-attenuation operation.
Bit 5/Receive Signaling Change Of State Event (RSCOS). Set when any channel selected by the receive-signaling change-
of-state interrupt-enable registers (RSCSE1 through RSCSE4) changes signaling state.
Bit 6/Timer Event (TIMER). Follows the error counter update interval as determined by the ECUS bit in the Error Counter
Configuration Register (ERCNT).
T1 Mode: Set on increments of one second or 42ms based on RCLK.
E1 Mode: Set on increments of one second or 62.5ms based on RCLK.
Bit 7/Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls below the
threshold set by the value in CCR4.4 through CCR4.7. The level must remain below the programmed threshold for
approximately 50ms for this bit to be set. This is a double interrupt bit.