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information.
Signal Name: A7/ALE(AS)
Signal Description: A7 or Address Latch Enable(Address Strobe)
Signal Type: Input
In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it
serves to demultiplex the bus on a positive-going edge.
Signal Name: WR*(R/W*)
Signal Description: Write Input(Read/Write)
Signal Type: Input
WR* is an active-low signal.
3.4 Extended System Information Bus
Signal Name: ESIBS0x
Signal Description: Extended System Information Bus Select 0
Signal Type: Input/Output
Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus
(ESIB) for more details.
Signal Name : ESIBS1x
Signal Description: Extended System Information Bus Select 1
Signal Type: Input/Output
Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus
(ESIB) for more details.
Signal Name: ESIBRDx
Signal Description: Extended System Information Bus Read
Signal Type: Input/Output
Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus
(ESIB) for more details.
3.5 JTAG Test Access Port Pins
Signal Name: JTRST
Signal Description: IEEE 1149.1 Test Reset
Signal Type: Input
JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to
high. This action will set the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST
low. JTRST is pulled HIGH internally via a 10k resistor operation.
Signal Name: JTMS
Signal Description: IEEE 1149.1 Test Mode Select
Signal Type: Input
This pin is sampled on the rising edge of JTCLK and is used to place the test-access port into the various defined IEEE 1149.1
states. This pin has a 10k pullup resistor.