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8.4 T1 Information Register
Register Name: INFO1
Register Description: Information Register 1
Register Address: 10h
Bit # 7 6 5 4 3 2 1 0
Name RPDV TPDV COFA 8ZD 16ZD SEFE B8ZS FBE
Default 0 0 0 0 0 0 0 0
Bit 0/Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
Bit 1/B8ZS Code Word Detect Event (B8ZS). Set when a B8ZS code word is detected at RPOS and RNEG independent of
whether the B8ZS mode is selected or not via T1TCR2.7. Useful for automatically setting the line coding.
Bit 2/Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in error.
Bit 3/Sixteen Zero Detect Event (16ZD). Set when a string of at least 16 consecutive zeros (regardless of the length of the
string) have been received at RPOSI and RNEGI.
Bit 4/Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the length of the
string) have been received at RPOSI and RNEGI.
Bit 5/Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or multiframe
alignment.
Bit 6/Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not meet the ANSI T1.403
requirements for pulse density.
Bit 7/Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403
requirements for pulse density.