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Register Name: RCICE3
Register Description: Receive Channel Idle Code Enable Register 3
Register Address: 86h
Bit # 7 6 5 4 3 2 1 0
Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
Default 0 0 0 0 0 0 0 0
Bits 0 to 7/Receive Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).
0 = do not insert data from the idle code array into the receive data stream
1 = insert data from the idle code array into the receive data stream
Register Name: RCICE4
Register Description: Receive Channel Idle Code Enable Register 4
Register Address: 87h
Bit # 7 6 5 4 3 2 1 0
Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Default 0 0 0 0 0 0 0 0
Bits 0 to 7/Receive Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32).
0 = do not insert data from the idle code array into the receive data stream
1 = insert data from the idle code array into the receive data stream