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24. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION
The DS21Q55 has the ability to generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in
length. This function is available only in T1 mode. To transmit a pattern, the user will load the pattern
to be sent into the transmit code definition registers (TCD1 and TCD2) and select the proper length of the
pattern by setting the TC0 and TC1 bits in the in-band code-control (IBCC) register. When generating a
1-, 2-, 4-, 8-, or 16-bit pattern both transmit code-definition registers (TCD1 and TCD2) must be filled
with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires TCD1 to be filled. Once
this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (T1CCR1.0) is
enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the
framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent.
An example: to transmit the standard loop-up code for channel service units (CSUs), which is a repeating
pattern of ...10000100001..., set TCD1 = 80h, IBCC = 0 and T1CCR1.0 = 1.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for loop-up
and loop-down code detection. The user will program the codes to be detected in the receive-up code-
definition (RUPCD1 and RUPCD2) registers and the receive-down code-definition (RDNCD1 and
RDNCD2) registers and the length of each pattern will be selected via the IBCC register. A third detector
(spare) is defined and controlled via the RSCD1/RSCD2 and RSCC registers. Both receive code-
definition registers are used together to form a 16-bit register when detecting a 16-bit pattern. Both
receive code-definition registers will be filled with the same value for 8-bit patterns. Detection of a 1-, 2-,
3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code-definition register to be filled. The
framer will detect repeating pattern codes in both framed and unframed circumstances with bit error rates
as high as 10E-2. The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns.
Writing the least significant byte of the receive code-definition register resets the integration period for
that detector. The code detector has a nominal integration period of 36ms. Hence, after about 36ms of
receiving a valid code, the proper status bit (LUP at SR3.5, LDN at SR3.6, and LSPARE at SR3.7 ) will
be set to a one. Normally codes are sent for a period of five seconds. It is recommended that the software
poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure that the code is
continuously present.