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Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated
information.
Signal Name: BPCLKx
Signal Description: Back Plane Clock
Signal Type: Output
A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name: RPOSOx
Signal Description: Receive Positive Data Output
Signal Type: Output
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
Signal Name: RNEGOx
Signal Description: Receive Negative Data Output
Signal Type: Output
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI.
Signal Name: RCLKOx
Signal Description: Receive Clock Output
Signal Type: Output
Buffered recovered clock from the network. This pin is normally tied to RCLKI.
Signal Name: RPOSIx
Signal Description: Receive Positive Data Input
Signal Type: Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.
Signal Name: RNEGIx
Signal Description: Receive Negative Data Input
Signal Type: Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.
Signal Name: RCLKIx
Signal Description: Receive Clock Input
Signal Type: Input
Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC pin high.
3.3 Parallel Control Port Pins
Signal Name: INT*
Signal Description: Interrupt
Signal Type: Output
Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.
Signal Name: TSTRST
Signal Description: 3-State Control and Device Reset
Signal Type: Input
A dual-function pin. A zero-to-one transition issues a hardware reset to the DS21Q55 register set. A reset clears all
configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will 3-state all output and I/O
pins (including the parallel control port). Set low for normal operation. Useful in-board level testing.