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ADDRESS R/W REGISTER NAME
REGISTER
ABBREVIATION
PAGE
C2 Receive FDL Match Register 1 RFDLM1 *
C3 Receive FDL Match Register 2 RFDLM2 *
C4 Test Register TEST *
C5 Interleave Bus Operation Control Register IBOC *
C6 Receive Align Frame Register RAF *
C7 Receive Nonalign Frame Register RNAF *
C8 Receive Si Align Frame RSiAF *
C9 Receive Si Nonalign Frame RSiNAF *
CA Receive Remote Alarm Bits RRA *
CB Receive Sa4 Bits RSa4 *
CC Receive Sa5 Bits RSa5 *
CD Receive Sa6 Bits RSa6 *
CE Receive Sa7 Bits RSa7 *
CF Receive Sa8 Bits RSa8 *
D0 Transmit Align Frame Register TAF *
D1 Transmit Nonalign Frame Register TNAF *
D2 Transmit Si Align Fra me TSiAF *
D3 Transmit Si Nonalign Frame TSiNAF *
D4 Transmit Remote Alarm Bits TRA *
D5 Transmit Sa4 Bits TSa4 *
D6 Transmit Sa5 Bits TSa5 *
D7 Transmit Sa6 Bits TSa6 *
D8 Transmit Sa7 Bits TSa7 *
D9 Transmit Sa8 Bits TSa8 *
DA Transmit Sa Bit Control Register TSACR *
DB BERT Alternating Word Count Rate BAWC *
DC BERT Repetitive Pattern Set Register 1 BRP1 *
DD BERT Repetitive Pattern Set Register 2 BRP2 *
DE BERT Repetitive Pattern Set Register 3 BRP3 *
DF BERT Repetitive Pattern Set Register 4 BRP4 *
E0 BERT Control Register 1 BC1 *
E1 BERT Control Register 2 BC2 *
E2 Test Register TEST *
E3 BERT Bit Count Register 1 BBC1 *
E4 BERT Bit Count Register 2 BBC2 *
E5 BERT Bit Count Register 3 BBC3 *
E6 BERT Bit Count Register 4 BBC4 *
E7 BERT Error Count Register 1 BEC1 *
E8 BERT Error Count Register 2 BEC2 *
E9 BERT Error Count Register 3 BEC3 *
EA BERT Interface Control Register BIC *
EB Error Rate Control Register ERC *
EC Number Of Errors 1 NOE1 *
ED Number Of Errors 2 NOE2 *
EE Number Of Errors Left 1 NOEL1 *
EF Number Of Errors Left 2 NOEL2 *
F0 Test Register TEST *
F1 Test Register TEST *
F2 Test Register TEST *
F3 Test Register TEST *
F4 Test Register TEST *
F5 Test Register TEST *