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information.
G.802 TIMING, E1 MODE ONLY Figure 35-17
NOTE:
1) RCHBLK or TCHBLK programmed to pulse high during timeslots 1 through 15, 17 through 25, and
bit 1 of timeslot 26.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31031 32
TS #
RSYNC
TSYNC
RCHCLK
TCHCLK
RCHBLK
TCHBLK
CHANNEL 26CHANNEL 25
LSB MSB
RCLK / RSYSCLK
TCLK / TSYSCLK
RSER / TSER
RCHCLK / TCHCLK
RCHBLK / TCHBLK
1 20