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Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated
information.
1.1 FEATURE HIGHLIGHTS
The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and
E1 transceivers plus many new features.
1.1.1 General
§ 27mm, 1.27 pitch BGA
§ 3.3V supply with 5V tolerant inputs and outputs
§ Pin compatible with DS21x5y family
§ Software compatible with the DS2155
§ Evaluation kits
§ IEEE 1149.1 JTAG-boundary scan
§ Driver source code available from the factory
1.1.2 Line Interface
§ Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,
6.276MHz, or 12.552MHz for T1-only operation
§ Fully software configurable
§ Short- and long-haul applications
§ Automatic receive sensitivity adjustments
§ Ranges include 0dB to -43dB or 0dB to -15dB for E1 applications; 0dB to -36dB or 0dB to -15dB
for T1 applications
§ Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
§ Internal receive termination option for 75O, 100O, and 120O lines
§ Monitor application gain settings of 20dB, 26dB, and 32dB
§ G.703 receive-synchronization signal-mode
§ Flexible transmit-waveform generation
§ T1 DSX-1 line build-outs
§ T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB
§ E1 waveforms include G.703 waveshapes for both 75O coax and 120O twisted cables
§ AIS generation independent of loopbacks
§ Alternating ones and zeros generation
§ Square-wave output
§ Open-drain output option
§ NRZ format option
§ Transmitter power-down
§ Transmitter 50mA short-circuit limiter with exceeded indication of current limit
§ Transmit open-circuit-detected indication
§ Line interface function can be completely decoupled from the framer/formatter
1.1.3 Clock Synthesizer
§ Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
§ Derived from recovered receive clock
1.1.4 Jitter Attenuator
§ 32-bit or 128-bit crystal-less jitter attenuator