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Register Name: PCLR3
Register Description: Per-Channel Loopback Enable Register 3
Register Address: 4Dh
Bit # 7 6 5 4 3 2 1 0
Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
Default 0 0 0 0 0 0 0 0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 17 to 24 (CH17 to CH24).
0 = loopback disabled
1 = enable loopback. Source data from the corresponding receive channel
Register Name: PCLR4
Register Description: Per-Channel Loopback Enable Register 4
Register Address: 4Eh
Bit # 7 6 5 4 3 2 1 0
Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Default 0 0 0 0 0 0 0 0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 25 to 32 (CH25 to CH32).
0 = loopback disabled
1 = enable loopback. Source data from the corresponding receive channel