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23.4 MCLK Prescaler
A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU
specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require
an accuracy of ±32ppm for T1 interfaces. A prescaler will divide the 16MHz, 8MHz, or 4MHz clock down to
2.048MHz. There is an onboard PLL for the jitter attenuator that will convert the 2.048MHz clock to a
1.544MHz rate for T1 applications. Setting JAMUX (LIC2.3) to a logic 0 bypasses this PLL.
23.5 Jitter Attenuator
The DS21Q55 contains an onboard jitter attenuator that can be set to a depth of either 32 bits or 128 bits
via the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander
are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the
attenuation are shown in Figure 14. The jitter attenuator can be placed in either the receive path or the
transmit path by appropriately setting or clearing the JAS bit (LIC1.3). Also, the jitter attenuator can be
disabled (in effect, removed) by setting the DJA bit (LIC1.1). Onboard circuitry adjusts either the
recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a
smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO. It is acceptable to
provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the
incoming jitter exceeds either 120UIpp (buffer depth is 128 bits) or 28UIpp (buffer depth is 32 bits), then
the jitter attenuator will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either
15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either
15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in Status Register 1 (SR1.4).
23.6 CMI (Code Mark Inversion) Option
The DS21Q55 provides a CMI interface for connection to optical transports. This interface is a unipolar
1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the
clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period.
CMI CODING Figure 25-3
Transmit and receive CMI is enabled via LIC4.7. When this register bit is set, the TTIP pin will output
CMI coded data at normal levels. This signal can be used to directly drive an optical interface. When
CMI is enable, the user can also use HDB3/B8ZS coding. When this register bit is set, the RTIP pin will
become a unipolar CMI input. The CMI signal will be processed to extract and align the clock with data.
01 1 1 0 0 1
CLOCK
DATA
CMI