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TRANSMIT SIDE TIMING Figure 35-18
NOTES:
1) TSYNC in frame mode (IOCR1.2 = 0).
2) TSYNC in multiframe mode (IOCR1.2 = 1).
3) TLINK is programmed to source just the Sa4 bit.
4) This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame.
5) TLINK and TLCLK are not synchronous with TSSYNC.
1 2 3 4 5 6 7 8 9 1011 12
1
3
TSSYNC
FRAME#
TSYNC
TSYNC
13
14 15 16
1 2 3 4 5
TLCLK
TLINK
14 15 16
6 7 8 9 10
3
2