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110 www.xilinx.com Development System Reference Guide
Chapter 4: PARTGen
R
• External Clock IOB pins:
♦ For Virtex, Virtex-E, Spartan-II, and Spartan-3E
GCLKBUF0=PAD#, GCLKBUF1=PAD#,
GCLKBUF2=PAD#, GCLKBUF3=PAD#
♦ For Virtex-II, Virtex-II Pro, and Virtex-4:
BUFGMUX0P=PAD#, BUFGMUX1P=PAD#,
BUFGMUX2P=PAD#, BUFGMUX3P=PAD#, BUFGMUX4P=PAD#,
BUFGMUX5P=PAD#,
BUFGMUX6P=PAD#, BUFGMUX7P=PAD#
• Block RAM:
NUM_BLK_RAMS=#
BLK_RAM_COLS=# BLK_RAM_COL0=# BLK_RAMCOL1=# BLK_RAM_COL2=#
BLK_RAM_COL_3=#
BLK_RAM_SIZE=4096x1 BLK_RAM_SIZE=2048x2 BLK_RAM_SIZE=512x8
BLK_RAM_SIZE=256x16
Block RAM locations are given with reference to CLB columns. In the following
example, Block RAM 5 is positioned in CLB column 32.
NUM_BLK_RAMS=10 BLK_RAM_COL_5=32 BLK_RAM_SIZE=4096X1
• Select RAM:
NUM_SEL_RAMS=# SEL_RAM_SIZE=#X#
• Select Dual Port RAM:
SEL_DP_RAM={TRUE|FALSE}
This field indicates whether the select RAM can be used as a dual port ram. The
assumption is that the number of addressable elements is reduced by half, that is, the
size of the select RAM in Dual Port Mode is half that indicated by SEL_RAM_SIZE.
• Speed grade information: SPEEDGRADE=#
• Typical delay across a LUT for each speed grade: LUTDELAY=#
• Typical IOB input delay: IOB_IN_DELAY=#
• Typical IOB output delay: IOB_OUT_DELAY=#
• Maximum LUT constructed in a slice:
MAX_LUT_PER_SLICE=#
(From all the LUTs in the slice)
• Max LUT constructed in a CLB: MAX_LUT_PER_CLB=#
This field describes how wide a LUT can be constructed in the CLB from the available
LUTs in the slice.