Xilinx 8.2i Life Jacket User Manual


 
98 www.xilinx.com Development System Reference Guide
Chapter 3: Tcl
R
# get project properties available
set props2 [project properties]
puts "Project Properties for top-level module $top" $props2
# inspect the current value for the following batch application options
set map_guide_mode [project get "MAP Guide Mode"]
puts "MAP Guide Mode = $map_guide_mode"
set par_guide_mode [project get "PAR Guide Mode"]
puts "PAR Guide Mode = $par_guide_mode"
# set batch application options :
# 1. set synthesis optimization goal to speed
# 2. ignore any LOCs in ngdbuild
# 3. perform timing-driven packing
# 4. use the highest par effort level
# 5. set the par extra effort level
# 6. pass "-instyle xflow" to the par command-line
# 7. generate a verbose report from trce
# 8. create the IEEE 1532 file during bitgen
project set "Optimization Goal" Speed
project set "Use LOC Constraints" false
project set "Perform Timing-Driven Packing and Placement" TRUE
project set "Place & Route Effort Level (Overall)" High
project set "Extra Effort (Highest (PAR level only)" "Continue on
Impossible"
project set "Other Place & Route Command Line Options" "-intsyle xflow"
project set "Report Type" "Verbose Report"
project set "Create IEEE 1532 Configuration File" TRUE
# run the entire xst-to-trce flow
process run "Implement Design"
# close project
project close
# open project again
project open
# alter some partition properties
partition rerun /stopwatch/sixty implementation
partition rerun /stopwatch/lsbled synthesis