Xilinx 8.2i Life Jacket User Manual


 
244 www.xilinx.com Development System Reference Guide
Chapter 12: TRACE
R
Clock Path: rclk_in to ffl_reg
Location Delay type Delay(ns) Logical Resource(s)
------------------------------------------------- -------------------
A8.I Tiopi 0.825 rclk_in
read_ibufg
CM_X1Y1.CLKIN net (fanout=1) 0.798 rclk_ibufg
CM_X1Y1.CLK90 Tdcmino -4.290 read_dcm
UFGMUX5P.I0 net (fanout=1) 0.852 rclk_90_dcm
BUFGMUX5P.O Tgi0o 0.589 read90_bufg
4.OTCLK1 net (fanout=2) 0.593 rclk_90
------------------------------------------------ --------------------
Total -0.633ns (-2.876ns logic, 2.243ns route)
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OFFSET OUT Constraint Examples
The following section describe specific examples of an OFFSET OUT constraint, as shown
in the Timing Constraints section of a timing report. For clarification, the OFFSET OUT
constraint information is divided into the following parts:
OFFSET OUT Header
OFFSET OUT Path Details
OFFSET OUT Detail Clock Path
OFFSET OUT Detail Path Data
OFFSET OUT Header
The header includes the constraint, the number of items analyzed, and number of timing
errors detected. See the PERIOD Header for more information on items analyzed and
timing errors.
Example:
====================================================================
Timing constraint: OFFSET = OUT 10 nS AFTER COMP "rclk_in" ;
50 items analyzed, 0 timing errors detected.
Minimum allowable offset is 9.835ns.
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