Xilinx 8.2i Life Jacket User Manual


 
Development System Reference Guide www.xilinx.com 417
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script
A script is a series of commands that automatically execute a complex
operation such as the steps in a design flow.
SDF (standard delay format)
Standard Delay Format (SDF) is an industry-standard file format for
specifying timing information. It is usually used for simulation.
seed
A seed is a random number that determines the order of the cells in
the design to be placed.
set/reset
This operation is made possible by the asynchronous set/reset
property. This function is also implemented by the Global Reset
STARTUP primitive.
shift register
A shift register is a register in which data is loaded in parallel and
shifted out of the register again. It refers to a chain of flip-flops
connected in cascade.
signal
A signal is a wire or a net. See “net.”
simulation
Simulation is the process of verifying the logic and timing of a design.
skew
Skew is clock delay. See clock skew.
slew rate
The slew rate is the speed with which the output voltage level
transitions from +5 V to 0 V or vice-versa. The slew rate determines
how fast the transistors on the outputs change states.
slice
Two slices form a CLB within Virtex and Spartan-II families.
speed
Speed is a function of net types, CLB density, switching matrices, and
architecture.
STARTUP symbol
The STARTUP symbol is a symbol used to set/reset all CLB and IOB
flip-flops.