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Development System Reference Guide www.xilinx.com 249
PERIOD Constraints
R
The Clock Uncertainty for an OFFSET constraint might be different than the clock
uncertainty on a PERIOD constraint for the same clock. The OFFSET constraint only looks
at one clock edge in the equation but the PERIOD constraints takes into account the
uncertainty on the clock at the source registers and the uncertainty on the clock at the
destination register therefore there are two clock edges in the equation.
Example:
----------------------------------------------------------------------
Slack: 8.175ns (requirement - (data path - clock skew
+ uncertainty))
Source: wr_addr[0] (FF)
Destination: fifo_ram/BU5/SP (RAM)
Requirement: 12.000ns
Data Path Delay: 3.811ns (Levels of Logic = 1)
clock skew: -0.014ns
Source Clock: wclk rising at 0.000ns
Destination Clock: wclk rising at 12.000ns
Clock Uncertainty: 0.000ns
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PERIOD Path Details
The first line is a link to the Constraint Improvement Wizard (CIW). The CIW gives
suggestions for resolving timing constraint issues if it is a failing path. The data path
section shows all the delays for each component and net in the path. The first column is the
Location of the component in the FPGA. It is turned off by default in TWX reports. The
next column is the Delay Type. If it is a net, the fanout is shown. The Delay names
correspond with the datasheet. For an explanation of the delay names, click on a delay
name for a description page to appear. Descriptions for Virtex-E , Virtex-II , Virtex-II Pro
and Spartan-II architectures are available.
The next columns are the Physical Resource and Logical Resource names. The Physical
name is the name of the component after mapping. This name is generated by the Map
process. It is turned off by default in TWX reports. The logical name is the name in the
design file. This is typically created by the synthesis tool or schematic capture program.