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406 www.xilinx.com Development System Reference Guide
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gate array
A gate array is part of the ASIC chip. A gate array represents a certain
type of gate repeated all over a VLSI-type chip. This type of logic
requires the use of masks to program the connections between the
blocks of gates.
global buffers
Global buffers are low-skew, high-speed buffers that connect to long
lines. They do not map logic.
There is one BUFGP and one BUFGS in each corner of the chip.
Primary buffers must be driven by an IOB. Secondary buffers can be
driven by internal logic or IOBs.
global Set/Reset net
A global Set/Reset net is a high-speed, no-skew dedicated net, which
reduces delays and routing congestion. This net accesses all flip-flops
on the chip and can reinitialize all CLBs and IOBs.
global 3-state net
A global 3-state net is a net that forces all device outputs to high-
impedance state unless boundary scan is enabled and executes an
EXTEST instruction.
GND pin
The GND pin is Ground (0 volts).
group
A group is a collection of common signals to form a bus. In the case of
a counter, for example, the different signals that produce the actual
counter values can be combined to form an alias, or group.
guide file
A guide file is a previously placed and routed NCP file that can be
used in a subsequent place and route operation.
guided design
Guided design is the use of a previously implemented version of a file
for design mapping, placement, and routing. Guided design allows
logic to be modified or added to a design while preserving the layout
and performance that have been previously achieved.