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Chapter 15: BSDLAnno
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For most Xilinx device families, the boundary scan architecture changes after the device is
configured because the boundary scan registers sit behind the output buffer and the input
sense amplifier:
BSCAN Register -> output buffer/input sense amp -> PAD
The hardware is arranged in this way so that the boundary scan logic operates at the I/O
standard specified by the design. This allows boundary scan testing across the entire range
of available I/O standards.
BSDLAnno Syntax
The following syntax creates a post-configuration BSDL file with BSDLAnno:
bsdlanno [options] infile outfile[.bsd]
options is one or more of the options listed in “BSDLAnno Options”.
infile is the design source file for the specified design. For FPGA designs, the infile is a
routed (post-PAR) NCD file. For CPLD designs, the infile is the design.pnx file.
outfile is the destination for the design-specific BSDL file with an optional .bsd extension.
The length of the BSDL output filename, including the .bsd extension, cannot exceed 24
characters.
BSDLAnno Input Files
BSDLAnno requires two input files to generate a post-configuration BSDL file:
• Pre-configuration BSDL (.bsd) file that is automatically read from the Xilinx
installation area.
• The routed .ncd file (FPGAs) or the .pnx file (CPLDs), which is specified as the infile.
BSDLAnno Output Files
The output from BSDLAnno is an ASCII (text) formatted BSDL file that has been modified
to reflect signal direction (input/output/bidirectional), unused I/Os, and other design-
specific boundary scan behavior.
BSDLAnno Options
This section provides information on the BSDLAnno command line options.
–s (Specify BSDL file)
–s [IEEE1149 | IEEE1532]
The –s option specifies the pre-configuration BSDL file to be annotated. IEEE1149 and
IEEE1532 versions of the pre-configuration BSDL file are currently available.
Note:
Most users require the IEEE1149 version.