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234 www.xilinx.com Development System Reference Guide
Chapter 12: TRACE
R
For errors in which the path delays are broken down into individual net and component
delays, the report lists each physical resource and the logical resource from which the
physical resource was generated.
As in the other three types of reports, descriptive material appears at the top. A timing
summary always appears at the end of the reports.
The following sample error report (error.twr) represents the output generated with this
TRACE command:
trce –e 3 ramb16_s1.ncd clkperiod.pcf –o error_report.twr
------------------------------------------------------------------
Xilinx TRACE
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
trce -e 3 ramb16_s1.ncd clkperiod.pcf -o error_report.twr
Design file: ramb16_s1.ncd
Physical constraint file: clkperiod.pcf
Device,speed: xc2v250,-5 (ADVANCED 1.84 2001-05-09)
Report level: error report
------------------------------------------------------------------
==================================================================
Timing constraint: TS01 = PERIOD TIMEGRP "clk" 10.333ns ;
0 items analyzed, 0 timing errors detected.
------------------------------------------------------------------
==================================================================
Timing constraint: OFFSET = IN 3.0 ns AFTER COMP "clk" TIMEGRP "rams" ;
18 items analyzed, 0 timing errors detected.
Maximum allowable offset is 9.224ns.
------------------------------------------------------------------
==================================================================
Timing constraint: TS02 = MAXDELAY FROM TIMEGRP "rams" TO TIMEGRP "pads"
8.0 nS ;
1 item analyzed, 1 timing error detected.
Maximum delay is 8.587ns.
------------------------------------------------------------------
Slack: -0.587ns (requirement - data path)
Source: RAMB16.A
Destination: d0
Requirement: 8.000ns
Data Path Delay: 8.587ns (Levels of Logic = 2)
Source Clock: CLK rising at 0.000ns