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Development System Reference Guide www.xilinx.com 175
PAR Reports
R
Number of LOCed IOBs 78 out of 80 97%
Number of RAMB16s 1 out of 12 8%
Number of SLICEs 26 out of 1408 1%
Overall effort level (-ol): High (set by user)
Placer effort level (-pl): High (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): High (set by user)
Starting initial Timing Analysis. REAL time: 31 secs
Finished initial Timing Analysis. REAL time: 31 secs
As shown in the next section, PAR reports different phases of the placer and identifies which
phase is being executed. The checksum number shown is for Xilinx debugging purposes only
and does not reflect the quality of the placer run. A running tally of the time transpired since
starting PAR is also shown in this section of the PAR report.
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:989a1f) REAL time: 43 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 43 secs
Phase 3.2
Phase 3.2 (Checksum:1c9c37d) REAL time: 47 secs
Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 47 secs
Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 47 secs
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 47 secs
Phase 7.8
Phase 7.8 (Checksum:9a609d) REAL time: 47 secs
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 47 secs
Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 47 secs
Phase 10.24
Phase 10.24 (Checksum:5f5e0f6) REAL time: 47 secs
Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 47 secs