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Development System Reference Guide www.xilinx.com 265
BitGen Options
R
DisableBandgap
Disables bandgap generator for DCMs to save power.
DONE_cycle
Selects the Startup phase that activates the FPGA Done signal. Done is delayed when
DonePipe=Yes.
DonePin
Adds an internal pull-up to the DONE Pin pin. The Pullnone setting disables the pullup.
Use this option only if you are planning to connect an external pull-up resistor to this pin.
The internal pull-up resistor is automatically connected if you do not use this option.
DonePipe
This option is intended for use with FPGAs being set up in a high-speed daisy chain
configuration.When set to Yes, the FPGA waits on the CFG_DONE (DONE) pin to go High
and then waits for the first clock edge before moving to the Done state.
Architectures: Virtex-II and Virtex-II Pro, Virtex-4,
Settings: No, Yes
Default: No
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: 1, 2, 3, 4, 5, 6
Default: 4
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullup, Pullnone
Default: Pullup
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: No, Yes
Default: No