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Development System Reference Guide www.xilinx.com 327
NetGen Timing Simulation Flow
R
When you run this option, NetGen checks that your library path is set up properly.
Following is an example of the appropriate path:
$XILINX/verilog/src/simprim
If you are using compiled libraries, this switch offers no advantage. If you use this switch,
do not use the –ul switch.
Note:
The –ism option is valid for post-translate (NGD), post-map, and post-place and route
simulation flows.
–ne (No Name Escaping)
By default (without the –ne option), NetGen “escapes” illegal block or net names in your
design by placing a leading backslash (\) before the name and appending a space at the
end of the name. For example, the net name “p1$40/empty” becomes “\p1$40/empty”
when name escaping is used. Illegal Verilog characters are reserved Verilog names, such as
“input” and “output,” and any characters that do not conform to Verilog naming
standards.
The –ne option replaces invalid characters with underscores so that name escaping does
not occur. For example, the net name “p1$40/empty” becomes “p1$40_empty” when
name escaping is not used. The leading backslash does not appear as part of the identifier.
The resulting Verilog file can be used if a vendor’s Verilog software cannot interpret
escaped identifiers correctly.
–pf (Generate PIN File)
The –pf option writes out a pin file—a Cadence signal-to-pin mapping file with a .pin
extension.
Note:
NetGen only generates a PIN file if the input is an NGM file.
–sdf_anno (Include $sdf_annotate)
-sdf_anno [true|false]
The –sdf_anno option controls the inclusion of the $sdf_annotate construct in a Verilog
netlist. The default for this option is true. To disable this option, use false.
Note:
The –sdf_anno option is valid for the timing simulation flow.
–sdf_path (Full Path to SDF File)
-sdf_path [path_name]
The –sdf_path option outputs the SDF file to the specified full path. This option writes the
full path and the SDF file name to the $sdf_annotate statement. If a full path is not
specified, it writes the full path of the current work directory and the SDF file name to the
$sdf_annotate statement.
Note:
The –sdf_path option is valid for the timing simulation flow.
–shm (Write $shm Statements in Test Fixture File)
The -shm option places $shm statements in the structural Verilog file created by NetGen.
These $shm statements allow NC-Verilog to display simulation data as waveforms. This
option is for use with Cadence NC-Verilog files only.