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Development System Reference Guide www.xilinx.com 143
Register Ordering
R
A CLB (Virtex/-E/-II/-II PRO or Spartan-II/IIE slice) has two flip-flops, so two register
bits can be mapped into one CLB. For PAR (Place And Route) to place a register in the most
effective way, you want as many pairs of contiguous bits as possible to be mapped
together into the same CLBs (for example, bit 0 and bit 1 together in one CLB, bit 2 and bit
3 in another).
MAP pairs register bits (performing register ordering) if it recognizes that a series of flip-
flops comprise a register. When you create your design, you can name register bits so they
are mapped using register ordering.
Note:
MAP does not perform register ordering on any flip-flops which have BLKNM, LOC, or RLOC
properties attached to them. The BLKNM, LOC, and RLOC properties define how blocks are to be
mapped, and these properties override register ordering.
To be recognized as a candidate for register ordering, the flip-flops must have the
following characteristics:
• The flip-flops must share a common clock signal and common control signals (for
example, Reset and Clock Enable).
• The flip-flop output signals must all be named according to this convention.
• Output signal names must begin with a common root containing at least one
alphabetic character.
The names must end with numeric characters or with numeric characters surrounded
by parentheses “( )”, angle brackets “< >”, or square brackets “[ ]”.
For example, acceptable output signal names for register ordering are as follows:
If a series of flip-flops is recognized as a candidate for register ordering, they are paired in
CLBs in sequential numerical order. For example, in the first set of names shown above,
data1 and data2, are paired in one CLB, while data3 and data4 are paired in another.
In the example below, no register ordering is performed, since the root names for the
signals are not identical
When it finds a signal with this type of name, MAP ignores the underscore and the
numeric characters when it considers the signal for register ordering. For example, if
signals are named data00_1 and data01_2, MAP considers them as data00 and data01 for
purposes of register ordering. These two signals are mapped to the same CLB.
MAP does not change signal names when it checks for underscores—it only ignores the
underscore and the number when it checks to see if the signal is a candidate for register
ordering.
data1 addr(04) bus<1>
data2 addr(08) bus<2>
data3 addr(12) bus<3>
data4 addr(16) bus<4>
data01
addr02
atod03
dtoa04