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Development System Reference Guide www.xilinx.com 399
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checksum
A checksum is a summation of bits or digits generated according to an
arbitrary formula used for checking data integrity. To verify that the
data represented by a checksum number has been entered correctly,
verify that the checksum number generated after processing is the
same as the initial number.
CLB
The Configurable Logic Block (CLB). Constitutes the basic FPGA cell.
It includes two 16-bit function generators (F or G), one 8-bit function
generator (H), two registers (flip-flops or latches), and
reprogrammable routing controls (multiplexers).
CLBs are used to implement macros and other designed functions.
They provide the physical support for an implemented and
downloaded design. CLBs have inputs on each side, and this
versatility makes them flexible for the mapping and partitioning of
logic.
CCLK pin
The CCLK pin is the XChecker pin that provides the configuration
clock for the device or devices during a download.
clock
A clock is a signal that represents the time that a wave stays at a High
or Low state. The rising and falling edges of a clock square wave
trigger the activity of the circuits.
clock buffer
A clock buffer is an element used to increase the current or drive of a
weak clock signal and consequently increase its fanout.
clock enable
A clock enable is a binary signal that allows or disallows synchronous
logic to change with a clock signal. When enabled, this control signal
permits a device to be clocked and to become active. There are four
different states. The two active High states are CE 0 disabled and CE
1 enabled. The two active Low states are CE
0 enabled and CE 1
disabled.
clock skew
Clock skew is the time differential between 2 or more destination pins
in a path.
CMOS
Complementary Metal Oxide Semiconductor (CMOS). Is an advanced
IC manufacturing process technology characterized by high
integration, low cost, low power, and high performance.