Filter
Top Products
238 www.xilinx.com Development System Reference Guide
Chapter 12: TRACE
R
Clock Path: clk to RAMB16.A
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
-------------------------------------------------------
IOB.I Tiopi 0.551 clk
clk
clk/new_buffer
BUFGMUX.I0 net e 0.100 clk/new_buffer
(fanout=1)
BUFGMUX.O Tgi0o 0.225 I$9
I$9
RAM16.CLKA net e 0.100 CLK
(fanout=1)
-------------------------------------------------------
Total 0.976ns (0.776ns logic, 0.200ns
route)
(79.5% logic, 20.5%
route)
------------------------------------------------------------------
==================================================================
Timing constraint: TS02 = MAXDELAY FROM TIMEGRP "rams" TO TIMEGRP "pads"
8.0 nS ;
1 item analyzed, 1 timing error detected.
Maximum delay is 8.587ns.
------------------------------------------------------------------
Slack: -0.587ns (requirement - data path)
Source: RAMB16.A
Destination: d0
Requirement: 8.000ns
Data Path Delay: 8.587ns (Levels of Logic = 2)
Source Clock: CLK rising at 0.000ns
Data Path: RAMB16.A to d0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -----------
RAMB16.DOA0 Tbcko 3.006 RAMB16
RAMB16.A
IOB.O1 net (fanout=1) e 0.100 N$41
IOB.PAD Tioop 5.481 d0
I$22
d0
------------------------------------------------- -----------
Total 8.587ns (8.487ns logic,
0.100ns route)
(98.8% logic, 1.2% route)
------------------------------------------------------------------
1 constraint not met.