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Development System Reference Guide www.xilinx.com 377
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TCL ASCII User (with text
editor)
TCL script file
TDR ASCII DRC Physical DRC report file
TEK Data PROMGen PROM-formatted file in
Tektronix’s TEKHEX format
TV ASCII NetGen Verilog test fixture file
TVHD ASCII NetGen VHDL testbench file
TWR ASCII TRACE Timing report file produced by
TRACE
TWX XML TRACE Timing report file produced by
TRACE. From this file, the user can
click any linked net or instance
names to navigate back to the net or
instance in the source design.
UCF ASCII User (with text
editor)
User-specified logical constraints
file
URF ASCII User (with text
editor)
User-specified rules file containing
information about the acceptable
netlist input files, netlist readers,
and netlist reader options
V ASCII NetGen Verilog netlist
VHD ASCII NetGen VHDL netlist
VM6 Design CPLDfit Output file from the CPLDfit
VXC ASCII NetGen Assertion file written for
Conformal-LEC equivalence
checking tool
XCT ASCII PARTGen File containing detailed
information about architectures
and devices
XTF ASCII Previous releases of
Xilinx Development
System
Xilinx netlist format file
XPI ASCII PAR File containing PAR run summary
Name Type Produced By Description