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46 www.xilinx.com Development System Reference Guide
Chapter 2: Design Flow
R
The following figure shows when you can perform functional and timing simulation:
The three primary simulation points can be expanded to allow for two post-synthesis
simulations. These points can be used if the synthesis tool cannot write VHDL or Verilog,
or if the netlist is not in terms of UniSim components. The following table lists all the
simulation points available in the HDL design flow.
These simulation points are described in the “Simulation Points” section of the Synthesis
and Simulation Design Guide.
Figure 2-11: Simulation Points for HDL Designs
Table 2-2: Five Simulation Points in HDL Design Flow
Simulation UniSim SimPrim SDF
RTL X
Post-Synthesis X
Functional Post-NGDBuild (Optional) X
Functional Post-MAP (Optional) X X
Post-Route Timing X X
X9243
HDL RTL
Simulation
Synthesis
Xilinx
Implementation
HDL Timing
Simulation
HDL
Design
Testbench
Stimulus
Post-Synthesis Gate-Level
Functional Simulation
CORE Generator
Modules
SimPrim
Library
LogiBLOX
Modules
UniSim
Library