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334 www.xilinx.com Development System Reference Guide
Chapter 22: NetGen
R
The figure below illustrates the NetGen Static Timing Analysis flow.
Input files for Static Timing Analysis
The Static Timing Analysis flow uses the following files as input:
• NCD file—This physical design file may be mapped only, partially or fully placed, or
partially or fully routed.
• PCF (optional)—This is a physical constraints file. If prorated voltage and
temperature is applied to the design, the PCF file must be included to pass this
information to NetGen. See “–pcf (PCF File)” for more information.
Output files for Static Timing Analysis
The Static Timing Analysis flow uses the following files as output:
• SDF file—This SDF 3.0 compliant standard delay format file contains delays obtained
from the input file.
• Verilog (.v) file—This is a IEEE 1364-2001 compliant Verilog HDL file that contains the
netlist information obtained from the input file. This file is a timing simulation model
and cannot be synthesized or used in any manner other than for static timing analysis.
This netlist uses simulation primitives, which may not represent the true
implementation of the device. The netlist represents a functional model of the
implemented design.
Syntax for NetGen Static Timing Analysis
The following command runs the NetGen Static Timing Analysis flow:
netgen -sta input_file[.ncd]
The input_file is the input file name and extension.
To get help on command line usage for equivalence checking, type:
netgen -h sta
Figure 22-6: Static Timing Analysis Flow for FPGAs
X10252
NCD
V/SDF
Static Timing Analysis Tool
NetGen
STA
Library
PCF