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Development System Reference Guide www.xilinx.com 243
OFFSET Constraints
R
----------------------------------------------------------------------
Slack: 2.684ns (requirement - (data path - clock path
- clock arrival + uncertainty))
Source: wclk_in (PAD)
Destination: ffl_reg (FF)
Destination Clock: rclk_90 rising at 2.500ns
Requirement: 4.000ns
Data Path Delay: 3.183ns (Levels of Logic = 5)
Clock Path Delay: -0.633ns (Levels of Logic = 3)
Clock Uncertainty: 0.000ns
Data Path: wclk_in to ffl_reg
Location Delay type Delay(ns) Logical Resource(s)
------------------------------------------------- -------------------
D7.I Tiopi 0.825 wclk_in
write_dcm/IBUFG
DCM_X0Y1.CLKIN net (fanout=1) 0.798 write_dcm/IBUFG
DCM_X0Y1.CLK0 Tdcmino -4.297 write_dcm/CLKDLL
BUFGMUX3P.I0 net (fanout=1) 0.852 write_dcm/CLK0
BUFGMUX3P.O Tgi0o 0.589 write_dcm/BUFG
SLICE_X2Y11.G3 net (fanout=41) 1.884 wclk
SLICE_X2Y11.Y Tilo 0.439 un1_full_st
SLICE_X2Y11.F3 net (fanout=1) 0.035 un1_full_st
SLICE_X2Y11.X Tilo 0.439 full_st_i_0.G_4.G_4.G_4
K4.O1 net (fanout=3) 1.230 G_4
K4.OTCLK1 Tioock 0.389 ffl_reg
------------------------------------------------- -------------------
Total 3.183ns (-1.616ns logic,
4.799ns route)