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Development System Reference Guide www.xilinx.com 3
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Preface
About This Guide
The Development System Reference Guide contains information about the command line
software programs in the Xilinx Development System. Most chapters are organized as
follows:
• A brief summary of program functions
• A syntax statement
• A description of the input files used and the output files generated by the program
• A listing of the commands, options, or parameters used by the program
• Examples of how to use the program
For an overview of the Xilinx Development System describing how these programs are
used in the design flow, see Chapter 2, “Design Flow”.
Guide Contents
The Development System Reference Guide provides detailed information about converting,
implementing, and verifying designs with the Xilinx command line tools. Check the
program chapters for information on what program works with each family of Field
Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD).
Following is a brief overview of the contents and organization of the Development System
Reference Guide:
Note:
For information on timing constraints, UCF files, and PCF files, see the Constraints Guide.
• Chapter 1, “Introduction” —This chapter describes some basics that are common to
the different Xilinx Development System modules.
• Chapter 2, “Design Flow”—This chapter describes the basic design processes: design
entry, synthesis, implementation, and verification.
• Chapter 3, “Tcl”—Tcl is designed to complement and extend the graphical user
interface (GUI). Xilinx Tcl commands provide a batch interface that makes it
convenient to execute the exact same script or steps over and over again.
• Chapter 4, “PARTGen”—PARTGen allows you to obtain information about installed
devices and families.
• Chapter 5, “Logical Design Rule Check”—The Logical Design Rule Check (DRC)
comprises a series of tests run to verify the logical design described by the Native
Generic Database (NGD) file.
• Chapter 6, “NGDBuild”—NGDBuild performs all of the steps necessary to read a
netlist file in EDIF format and create an NGD (Native Generic Database) file
describing the logical design reduced to Xilinx primitives.