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Development System Reference Guide www.xilinx.com 273
BitGen Options
R
Note: In modes where Cclk is an output, the pin is driven by an internal oscillator.
TckPin
Adds a pull-up, a pull-down or neither to the TCK pin, the JTAG test clock. Selecting one
setting enables it and disables the others. The Pullnone setting shows there is no
connection to either the pull-up or the pull-down.
TdiPin
Adds a pull-up, a pull-down, or neither to the TDI pin, the serial data input to all JTAG
instructions and JTAG registers. Selecting one setting enables it and disables the others.
The Pullnone setting shows there is no connection to either the pull-up or the pull-down.
TdoPin
Adds a pull-up, a pull-down, or neither to the TdoPin pin, the serial data output for all
JTAG instruction and data registers. Selecting one setting enables it and disables the
others. The Pullnone setting shows there is no connection to either the pull-up or the pull-
down.
TmsPin
Adds a pull-up, pull-down, or neither to the TMS pin, the mode input signal to the TAP
controller. The TAP controller provides the control logic for JTAG. Selecting one setting
enables it and disables the others. The Pullnone setting shows there is no connection to
either the pull-up or the pull-down
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullup, Pulldown, Pullnone
Default: Pullup
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullup, Pulldown, Pullnone
Default: Pullup
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullup, Pulldown, Pullnone
Default: Pullup
Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4,
Spartan-II, Spartan-IIE, Spartan-3, Spartan-3E
Settings: Pullup, Pulldown, Pullnone
Default: Pullup