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328 www.xilinx.com Development System Reference Guide
Chapter 22: NetGen
R
–ul (Write uselib Directive)
The –ul option causes NetGen to write a library path pointing to the SimPrim library into
the output Verilog (.v) file. The path is written as shown below:
uselib dir=$XILINX/verilog/src/simprims libext=.v
$XILINX is the location of the Xilinx software.
If you do not enter a –ul option, the ‘uselib line is not written into the Verilog file.
Note:
A blank ‘uselib statement is automatically appended to the end of the Verilog file to clear out
the ‘uselib data. If you use this option, do not use the –ism option.
Note: The –ul option is valid for SIMPRIM-based functional simulation and timing simulation flows;
although not all simulators support the ‘uselib directive. Xilinx recommends using this option
with caution.
–vcd (Write $dump Statements In Test Fixture File)
The –vcd option writes $dumpfile/$dumpvars statements in testfixture. This option is for
use with Cadence Verilog files only.
VHDL-Specific Options for Functional and Timing Simulation
This section describes the VHDL-specific command line options for timing simulation.
–a (Architecture Only)
By default, NetGen generates both entities and architectures for the input design. If the –a
option is specified, no entities are generated and only architectures appear in the output.
–ar (Rename Architecture Name)
-ar architecture_name
The –ar option allows you to rename the architecture name generated by NetGen. The
default architecture name for each entity in the netlist is STRUCTURE.
–rpw (Specify the Pulse Width for ROC)
–rpw roc_pulse_width
The –rpw option specifies the pulse width, in nanoseconds, for the ROC component. You
must specify a positive integer to simulate the component. This option is not required. By
default, the ROC pulse width is set to 100 ns.
–tpw (Specify the Pulse Width for TOC)
–tpw toc_pulse_width
The –tpw option specifies the pulse width, in nanoseconds, for the TOC component. You
must specify a positive integer to simulate the component. This option is required when
you instantiate the TOC component (for example, when the global set/reset and global 3-
State nets are sourceless in the design).