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Development System Reference Guide www.xilinx.com 145
Simulating Map Results
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In the EXACT mode the mapping in the guide file is followed exactly. Any logic in the
input NGD file that matches logic mapped into the physical components of the NCD guide
file is implemented exactly as in the guide file. Mapping (including signal to pin
assignments), placement and routing are all identical. Logic that is not matched to any
guide component is mapped by a subsequent mapping step.
If there is a match in EXACT mode, but your constraints would conflict with the mapping
in the guide file component, an error is posted. If an error is posted, you can do one of the
following:
• Modify the constraints to eliminate conflicts
• Change to the LEVERAGE guide mode (which is less restrictive)
• Modify the logical design changes to avoid conflicts
• Stop using guided design
In the LEVERAGE mode, the guide design is used as a starting point in order to speed up
the design process. However, in cases where the guided design tools cannot find matches
or your constraints rule out any matches, the logic is not guided. Whenever the guide
design conflicts with the your mapping, placement or routing constraints, the guide is
ignored and your constraints are followed.
Because the LEVERAGE mode only uses the guide design as a starting point for mapping,
MAP may alter the mapping to improve the speed or density of the implementation (for
example, MAP may collapse additional gates into a guided CLB).
Note:
Support for the leverage guide flow (–gm incremental), without a timing-driven map run of
your design, specified with the map –timing option, will not be supported in future releases of Xilinx
software.
For Spartan and Virtex/-E/-II/-II PRO devices, MAP uses the NGM and the NCD files as
guides. You do not need to specify the NGM file on the command line. MAP infers the
appropriate NGM file from the specified NCD file. If MAP does not find an NGM file in
the same directory as the NCD, it generates a warning. In this case, MAP uses only the
NCD file as the guide file.
Note:
Guided mapping is not recommended for most HDL designs. Guided mapping depends on
signal and component names, and HDL designs often have a low match rate when guided. The
netlist produced after re-synthesizing HDL modules usually contains signal and instance names that
are significantly different from netlists created by earlier synthesis runs. This occurs even if the
source level HDL code contains only a few changes.
Simulating Map Results
When simulating with NGM files, you are not simulating a mapped result, you are
simulating the logical circuit description. When simulating with NCD files, you are
simulating the physical circuit description.
MAP may generate an error that is not detected in the back-annotated simulation netlist.
For example, after running MAP, you can run the following command to generate the
back-annotated simulation netlist:
netgen mapped.ncd mapped.ngm –o mapped.nga