Xilinx 8.2i Life Jacket User Manual


 
228 www.xilinx.com Development System Reference Guide
Chapter 12: TRACE
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Following is an example of clock-to-output propagation delays in the data sheet
report:
Clock ck1_i to Pad
------------ ---+----------+
|clk (edge)|
Destination Pad |to PAD |
------------- --+----------+
out1_o | 16.691(R)|
------------- --+----------+
Clock to Setup on destination clock ck2_i
----- -----+-------+--------+--------+--------+
|Src/Dest |Src/Dest | Src/Dest| Src/Dest|
Source Clock|Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
-----------+-------+--------+--------+--------+
ck2_i | 12.647 | | | |
ck1_i |10.241 | | | |
-- --------+-------+--------+--------+--------+
The maximum propagation delay from each device input to each device output is
reported if a combinational path exists between the device input and output. When
two or more paths exist between a device input and output, the worst-case
propagation delay is reported. One worst-case propagation delay is reported for every
input and output combination in the design.
Following are examples of input-to-output propagation delays:
Pad to Pad
-----------------------------------------------
Source Pad |Destination Pad|Delay |
-------------+---------------+-------+
BSLOT0 |D0S |37.534 |
BSLOT1 |D09 |37.876 |
BSLOT2 |D10 |34.627 |
BSLOT3 |D11 |37.214 |
CRESETN |VCASN0 |51.846 |
CRESETN |VCASN1 |51.846 |
CRESETN |VCASN2 |49.776 |
CRESETN |VCASN3 |52.408 |
CRESETN |VCASN4 |52.314 |
CRESETN |VCASN5 |52.314 |
CRESETN |VCASN6 |51.357 |
CRESETN |VCASN7 |52.527 |
-------------+-------------+---------
User-Defined Phase Relationships
Timing separates clock-to-output and maximum propagation delay ranges for user-
defined internal clocks in the data sheet report. User-defined external clock
relationships shall not be reported separately. They are broken out as separate external
clocks.