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180 www.xilinx.com Development System Reference Guide
Chapter 9: PAR
R
Xplorer
Xplorer is a TCL script that seeks the best design performance using ISE implementation
software. After synthesis generates an EDIF or NGC (XST) file, the design is ready for
implementation. During this phase, you can use Project Navigator or the command line to
manually apply design constraints and explore different implementation tool settings for
achieving your timing goals; alternatively, you can use Xplorer. Xplorer is designed to help
achieve optimal results by employing smart constraining techniques and various physical
optimization strategies. Because no unique set of ISE options or timing constraints works
best on all designs, Xplorer finds the right set of implementation tool options to either meet
design constraints or find the best performance for the design. Hence, Xplorer has two
modes of operation: Best Performance Mode and Timing Closure Mode.
Xplorer support is available for the following Xilinx FPGA architectures:
• Virtex
™
-II Pro, Virtex
™
-II Pro X
• Virtex
™
-4 /FX/LX/SX
• Virtex
™
-5 LX
• Spartan
™
-3, Spartan
™
-3E, Spartan
™
-3L
Best Performance Mode
In this mode, Xplorer optimizes design performance for a user-specified clock domain,
allowing easy evaluation of the maximum achievable performance. You specify the design
name and a single clock to optimize. Xplorer implements the design with different
architecture-specific optimization strategies in conjunction with timing-driven place and
route (PAR). When the -clk option is specified, it tightens or relaxes the timing constraints
depending on whether or not the frequency goal is achieved. Xplorer estimates the starting
frequency based on pre-PAR timing data. Adjusting timing constraints such that PAR is
neither under nor over-constrained, enables Xplorer to deliver optimal design
performance.
In addition to timing constraints, Xplorer also uses physical optimization strategies such as
global optimization and timing-driven packing and placement. Global optimization
performs pre-placement netlist optimizations on the critical region, while timing-driven
packing and placement provides closed-loop packing and placement such that the placer
can recommend logic packing techniques that deliver optimal placement. If the design has
a User Constraints File (UCF), Xplorer optimizes for the user constraints on the specified
clock domain.
Following is sample command line syntax for Best Performance Mode. For a complete list
of Xplorer options, see “Xplorer Options.”
Example:
xplorer.tcl <design_name> -clk <clock_name> –p <part_name>
Description: design_name specifies the name of the top-level EDIF or NGC file.
clock name, specified with the -clk option, specifies the name of the
clock to optimize.
part_name, specified with the -p option, specifies the Xilinx part
name.