Filter
Top Products
Development System Reference Guide www.xilinx.com 281
BSDLAnno File Composition
R
"P151,P158,P166,P172,P182,P190,P196,P204,P211,P219," &
"P227,P233)," &
"INIT_P123:P123," &
"IO_P3:P3," &
"IO_P4:P4," &
"IO_P5:P5," &
"IO_P6:P6," &
BSDLAnno does not modify the package pin-mapping.
USE Statement
The USE statement calls VHDL packages that contain attributes, types, and constants that
are referenced in the BSDL file.
For example (from the xcv50e_pq240.bsd file):
use STD_1149_1_1994.all;
BSDLAnno does not modify USE statements.
Scan Port Identification
The scan port identification identifies the following JTAG pins: TDI, TDO, TMS, TCK and
TRST.
Note:
TRST is an optional JTAG pin that is not used by Xilinx devices.
For example (from the xcv50e_pq240.bsd file):
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (33.0e6, BOTH);
BSDLAnno does not modify the Scan Port Identification.
TAP Description
The TAP description provides additional information on the JTAG logic of a device.
Included are the instruction register length, instruction opcodes, and device IDCODE.
These characteristics are device-specific and may vary widely from device to device.
For example (from the xcv50e_pq240.bsd file):
attribute COMPLIANCE_PATTERNS of XCV50E_PQ240 : entity is
attribute INSTRUCTION_LENGTH of XCV50E_PQ240 : entity is 5;
attribute INSTRUCTION_OPCODE of XCV50E_PQ240 : entity is
attribute INSTRUCTION_CAPTURE of XCV50E_PQ240 : entity is "XXX01";
attribute IDCODE_REGISTER of XCV50E_PQ240 : entity is
BSDLAnno does not modify the TAP Description.