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72 www.xilinx.com Development System Reference Guide
Chapter 3: Tcl
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component_name specifies the name of the components to be disabled.
enable_constraints (enable constraints for analysis)
The timing_analysis enable_constraints command enables the specified timing constraints
for the analysis.
% timing_analysis enable_constraints <analysis_name> <timing_constraint_specs>
timing_analysis is the name of the Xilinx Tcl command.
enable_constraints is the name of the timing_analysis subcommand.
analysis_name specifies the name of the analysis generated previously with the
timing_analysis new command.
timing_constraint_specs specifies the names and specs of the constraints to be enabled for
analysis.
enable_cpt (enable components for path tracing control)
The timing_analysis enable_cpt command enables specified components associated with a
path tracing control for a timing path analysis.
% timing_analysis enable_cpt <analysis_name> <cpt_symbol> <component_name>
timing_analysis is the name of the Xilinx Tcl command.
enable_cpt is the name of the timing_analysis subcommand.
analysis_name specifies the name of the analysis generated previously with the
timing_analysis new command.
cpt_symbol specifies a path tracing control that determines whether associated components
are considered for the timing path analysis.
component_name specifies the name of the components to enable.
Example: % timing_analysis disable_cpt stopwatch_timing
reg_sr_clk “ureg_1 ureg_2 ureg_3”
Description: In this example, the specified components, ureg_1, ureg_2, and
ureg_3 are disabled for the timing path analysis.
Tcl Return: Number of components that were disabled.
Example: % timing_analysis enable_constraints
stopwatch_timing “TS_clk=PERIOD TIMEGROUP\”sclk\”
20 ns HIGH 50.00000%;”
Description: In this example, the specified timing constraint is enabled for
analysis.
Tcl Return: Number of enabled constraints.